16/20-bit stereo audio codec PCM3002

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Abstract: PCM3002 is a 16/20-bit stereo audio codec chip from TI. The performance characteristics and working principle of the chip are briefly analyzed, and the typical application circuit of PCM3002 is given.

Keywords: PCM3002; stereo; codec

1 Overview

The PCM3002 is a low power monolithic stereo audio codec with unipolar analog voltage input and output. The ADC and DAC are capable of 64x oversampling delta-sigma modulation. The ADC includes a digital decimation filter and the DAC includes an 8x oversampling interpolation filter. The DAC also has functions such as digital attenuation, de-emphasis, infinite zero detection, and software mute. It operates in left and right aligned formats and supports the IIS data format. The PCM3002 has a power-down mode that can be independently operated on the ADC and DAC. The programming function of the PCM3002 is controlled by software. In engineering applications, the chip can be used as an audio analog input and output of a digital signal processor (DSP). It has the advantages of simple structure, easy software control, and saving layout space. The main features of PCM3002 are as follows:

● Monolithic 20-bit delta-sigma ADC and DAC;

● 16/20 bit data input/output;

● Stereo ADC: unipolar voltage input; 64 times oversampling; THD+N (total harmonic distortion + noise): -86dB; SNR: 90dB; dynamic range: 90dB;

    ● Stereo DAC: unipolar voltage output; analog low-pass filter; 64 times oversampling; THD+N: -86dB; SNR: 94dB; dynamic range: 94dB;

●Special performance: digital de-emphasis; 256-level digital attenuation; software mute; digital loopback; power-down: ADC/DAC independent;

● sampling rate: up to 48kHz;

● System clock: 256fs, 384fs, 512fs;

● Single power supply + 3V power supply.

2 internal structure and pin function

Figure 1 shows a functional diagram of the PCM3002. After the collected analog audio signal passes through the analog front end, it is sent to the delta-sigma modulator and the digital decimation filter, and then modulated and filtered to be output in digital form. The input digital audio signal is passed through a digital interpolation filter and a multi-stage delta-sigma modulator, and then low-pass filtered and output to an external device in an analog form.

The PCM3002 is available in a SSOP-24 package with pinouts as shown in Figure 2.

3 PCM audio interface

The 4-wire digital audio interface of the PCM3002 includes: LRCIN, BCKIN, DIN, DOUT. It can use 4 data input/output formats (Format 0 to 3). In software mode, these formats are selected via software register 3.

    In one clock, the PCM3002 can use 32, 48, 64-bit clocks (BCKIN). When using the 32-bit clock LRCIN, only the 16-bit data format can be selected. The audio data input and output format is shown in Figure 3.

4 system clock

The system clock frequency of the PCM3002 must be 256fs, 384fs or 512fs, where fs is the audio sampling frequency. The system clock is input through the SYSCLK pin. The PCM3002 also has a system clock detection circuit that automatically detects if the system clock is operating at 256fs, 384fs or 512fs. When the system clock uses 384fs or 512fs, it automatically separates it into 256fs. The 256fs clock is used to manipulate the digital filter and the delta-sigma modulator.

4.1 Power-on reset

The PCM3002 has an internal power-on reset circuit. A power-on reset is generated when SYSCLK is active and VDD > 2.2V. The initialization sequence takes 1024 SYSCLK cycles to complete.

4.2 External reset

The PCM3002 has a reset pin RST. When SYSCLK is asserted, the external reset signal must drive RST low for at least 40ns to initialize the reset sequence. Initialization begins on the rising edge of RST and requires 1024 SYSCLK cycles to complete.

image 3

    4.3 Digital audio system synchronization

The PCM3002 synchronizes it with the system clock by operating LRCLK. LRCIN does not require any special phase relationship with the system clock, but must be synchronized. If the phase jitter on LRCIN changes the synchronization between the system clock and LRCIN more than 6 bit clock BCKIN in one sampling period, the internal operation of the DAC will stop within 1/fs, and the analog output will also be forced. To positive and negative zero (0.5VCC)? Until the system clock is synchronized to LR-CLK after the tDACDLY2 delay time. At the same time, the internal operation of the ADC will also stop within 1/fs, and the digital output code will also be set to positive and negative zeros until synchronization occurs after the tADCDLY2 delay time. If the LRCIN is synchronized to the system clock within 5 or fewer bit clocks, its operation will continue.

4.4 Zero mark output

The 16-pin ZFLG is an infinite zero detection flag. When the input data remains at 65536 BCKIN periods, ZFLG is low, otherwise ZFLG is high impedance.

5 operation control

In the software mode, the PCM3002 is controlled by the 3-wire serial interface MC, MD, ML. The special function of PCM3002 is realized by setting four 16-bit program registers. The program register structure is shown in Figure 4.

6 Typical applications

As a stereo multimedia digital codec, the PCM3002 samples analog signals through a voice input interface and then converts them into digital signals for processing by a microprocessor such as a DSP. After the microprocessor processes the data, it is converted into an analog signal output by the PCM3002, so that the user can directly hear it from the voice output interface.

    The input and output ports of the PCM3002 are available in an industry standard 3.5MM stereo interface. It can be widely used in the application design of multimedia audio-visual equipment and consumer products. Figure 5 shows a typical application circuit for the PCM3002.

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