Detailed requirements for PLD development tools for SoPC application design
For the development of programmable system-on-chip (SoPC), relying solely on programmable devices (PLDs) in terms of scale and speed, relying on easy-to-use embedded processor cores, and relying on other IP cores alone is not enough. . By addressing system-level complex issues and making PLD technology profitable in terms of time to market, a clear system-level construction approach is required.
In the past, PLD users loved the integrated features of MAX+PLUS II (a fully integrated design entity, including design input, synthesis, simulation, place and route, and timing analysis). Today, those users are also the best integrated. Tools, best simulation tools, and the best timing analysis tools. PLD place-and-route tools must meet these ever-changing requirements in a way that makes the entire design approach more directional in the direction of an application-specific integrated circuit (ASIC). If this new PLD design method is properly constructed, it will facilitate the application of IP cores faster than ASIC technology, and support the flexibility and customization capabilities that only programmable technology can provide.
It is now common practice to use IP cores in high-density devices. Although users have used bus interface functions (such as the 66 MHz PCI bus) and DSP functions (such as FIR filters) for several years, the application of IP cores has recently seen three basic changes. The first is that today's dedicated programmers have powerful features and flexibility. For example, the new FIR compiler includes a built-in coefficient generator that supports 4-bit to 32-bit coefficient precision, and can be designed with any number of taps. The compiler also supports equally spaced rounding, interpolation, and serial and parallel algorithmic structure options, allowing users to optimize filters for their performance and layout area requirements, and can be easily modified and reevaluated. Filters to meet system requirements.
The second important change in the way to enhance design is the interface that is now available for various industry standard development tools. For example, the current FIR compiler can also generate simulation models in MATLAB, Simulink, VHDL, and Verilog HDL formats to more closely connect with the various powerful tools described above. Similar application compilers for DSP applications such as Reed-Solomon error correction algorithms are also under development.
The third major change related to the application of the IP core is the emergence of embedded processors optimized for PLDs. The potential of SoPC design capabilities is truly possible only with high-performance processors. In an ideal development environment, the designer will simply write the C code that embody the system specification. Then, the intelligent development tool will divide some algorithms in the embedded processor and integrate the rest of the algorithms into Going in programmable logic. However, unfortunately, existing tools have not reached such advanced levels, and integrating embedded processors in PLDs will increase the complexity of the design. New development methods must address issues such as modeling, processor integration, and PLD design input, and intelligently develop various bus interfaces to optimize system performance.
To optimize system-level solutions, development tools must provide an accurate and complete model of how the processor core interacts with memory and peripheral I/O modules. Designing with a hard core processor typically requires a processor bus function module that describes a particular system bus operation, a timing relationship, and an interface between the internal processor module and other modules. Using a soft core processor requires a correct behavioral model to verify that the specific implementation within the PLD meets the timing specifications of the processor subsystem. The entire SoPC design process must support VHDL or Verilog simulation, behavioral simulation, and VHDL and Verilog test tools.
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