Innovative MOSFET package simplifies circuit design for power supplies

Probe domestic double-head probe 038-BB-5.7L The shape of the two ends of the needle is outside the pointed needle

SR05 SOT143 package 5V ESD electrostatic protection

MOS power IC full range

At present, one of the main challenges faced by power supply engineers is that as the functionality increases, the size of commercial electronic products continues to shrink, leaving less room for power circuits. One way to solve this problem is to take advantage of advances in MOSFET technology and packaging. By adopting higher performance MOSFETs in smaller packages, one trend in the industry is to shift from standard lead packages such as SO-8 to power packages with bottom drain pads. For high current applications, a common 6mm x 5mm package is available, such as PowerPAK® SO-8. But for smaller current applications, the trend is to shift to a 3mm x 3mm power package like the PowerPAK 1212-8. In this type of package, RDS(on) is low enough that this type of chip can be used in 10A DC-DC applications in notebook computers.

Although the 3mm x 3mm power package has greatly reduced the space used by DC-DC circuits, there is still a chance to reduce the space used and increase the power density. One way to achieve this is to replace discrete monolithic MOSFETs with packages that combine two devices. SO-8 dual-chip power MOSFETs have been in use for a long time, but usually only handle load currents below 5A. This is perfectly fine for 5V and 3.3V power rails in netbooks and laptops, but for load currents. A system of 10A or higher is obviously too low.

Figure 1

That's why manufacturers are trying to design a two-chip power package for MOSFETs because they greatly increase the maximum possible current and are better than traditional surface mount packages. Using the basic principle of this power package, two separate chips are packaged into one package, which reduces the area required for the power circuit.

PowerPAIR is one such package type that is smaller than the single-chip power 6 x 5 package (PowerPAK SO-8) and has a maximum current of 15A. In a notebook computer, generally such a large load current will be used in two power 6 x 5 packages, counting the area of ​​the wire and the label, and the position of the two devices, occupying more than 60mm2. The two-chip power package measures 6.0mm x 3.7mm and occupies 22mm2 on the board. Being able to reduce board space by 63% is very helpful for power engineers because they have less space for power circuit design. With the traditional SO-8 dual-chip power package, it is impossible to achieve such a big advantage.

Compared to two 6 x 5 power packages or two SO-8 packages, this device saves space and simplifies design, saving more space than two 3 x 3 power packages. The two-chip power package makes it easy to replace two 3x3 packages with one device, and even save wiring and marking space on the PCB, as shown in Figure 1. Therefore, for 5A~15A DC-DC applications, using this device is a very reasonable design step and one of the ways to increase the power density.

The PowerPAIR dual-chip power package uses an asymmetrical structure similar to a DC-DC buck converter, allowing optimized high-side and low-side devices to occupy the same package. As shown in Figure 2, the low-side MOSFET has a lower on-resistance than the high-side MOSFET, which results in inconsistent pad areas.

Figure II

In fact, the on-resistance of the low-side MOSFET is a key feature of the device. Even if the package size becomes smaller, it is possible to reduce the RDS(on) to less than 5mΩ at a voltage of up to 4.5V. This helps increase efficiency at maximum load conditions and allows the device to operate at lower temperatures, even at small sizes.

Another benefit of this device is wiring. As can be seen in Figure 2, the package pins allow it to be easily integrated into the buck converter design. More specifically, the input to the device is on one side and the output is on the other side. Pins 2 and 3 correspond to the VIN of the DC-DC circuit and are the drain of the high-side MOSFET. The small pad is also the drain pad of the high side component. The larger pad is the larger the pad of the circuit's switching node, where the drain of the high-side MOSFET's source and low-side MOSFET is internally connected to the device. This node will be connected to the inductor. Finally, ground is pins 4 and 5 and is the source of the low-side MOSFET. Pins 1 and 6 are connected to the gates of the high-side and low-side MOSFETs, respectively. This wiring is simple and reduces the chance of wiring errors when using two devices. Additional PCB traces are required when combining multiple devices, which also reduces the parasitic inductance associated with such PCB traces: the last benefit of switching to a smaller form factor dual-chip power package is achievable Efficiency can help increase power density. The device is mounted on a single-phase buck converter evaluation board as follows.
VIN = 12 V, VOUT = 1.05 V, VDRIVE = 5.0V, fsw = 300 kHz, IOUT max. = 15 A
Efficiency is measured over the entire power range. At 15A, the efficiency is 87% and the case temperature of the device is just below 70 °C. The peak efficiency is higher than 91.5%. This performance helps reduce power loss, save energy in medical systems, and enables small form factor designs.

Figure III

The two-chip asymmetric power package in a 6.0mm x 3.7mm form factor is a significant advancement in MOSFET packaging technology. This package enables engineers to improve power supply performance, reduce size, and simplify design while achieving the high efficiency or performance required by today's consumer electronics.