Intel Fellow: 3nm will be Silicon Process Limit

According to Intel’s academician, Paolo Gargini, ITRS chairman and director of the Intel Technology and Manufacturing Group, said that Intel has not yet developed a low-leakage device that can save energy by one to two orders of magnitude.

"Maybe by 2025, we can overcome all difficulties." Gargini said.

Therefore, in the next decade, the traditional lithography technology will exist, "We can still follow Moore's Law to 10nm or even smaller, but when it comes to 1nm, 2nm or 3nm, maybe everything will change.

In the past 20 years, Intel has taken a series of innovations to solve the problems of silicon materials, including strained silicon, high-k metal grids, and EUV technologies, to some extent overcome the limitations of silicon technology, but now, it is close to The limit of silicon material.

Today, Intel has been widely selecting materials for the post-silicon era, including III-V compounds such as QWFETs and tunnel diodes.