MIPI display standard for mobile internet devices
As mobile Internet devices become more popular, more and more vendors are racing to design the latest and most fashionable products. Low power consumption is always the most important thing for handheld devices, including the power consumption of their display components. According to market research firm iSuppli, Intel's processors for these devices account for half of the market. To replace the traditional, outdated RGB parallel bus, Intel used the LVDS and MIPI DSI bus interfaces in the recently released Moorestown processor.
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MIPI DSI is the latest display standard for mobile handsets. By configuring a scalable data channel, the interface can achieve a 3Gb/s data transfer rate, using low-voltage swing differential signals with very low output signal levels. The ECC and CRC checksums are also embedded in the data message to allow the receiver to perform error correction and recovery.
Applications are evolving Over the past few years, as MIPI DSI and DCS standards have matured, display manufacturers have begun to follow these standards in their products. Due to the complexity of mixed-signal designs and the uncertainty of rising market demand, mobile Internet device manufacturers are only able to obtain a few displays that integrate MIPI interfaces. Initially, most display manufacturers preferred the old and new standard bridging solutions before producing integrated MIPI-enabled displays, which could be used to test the market's reaction by converting high-speed serial interfaces to traditional parallel RGB interfaces.
As shown in Figure 1, MIPI supports the following two display standards.
Figure 1 (a) MIPI video mode working block diagram (b) MIPI DCS command mode block diagram
1 DSI video mode This mode of operation is similar to the traditional RGB interface, the host needs to continuously refresh the display. Since the synchronization information is transmitted without using a dedicated data signal, the control signal and the RGB data are transmitted in the form of a message through the MIPI bus. Because the host needs to periodically refresh the display, the display does not require a frame buffer.
2 DCS command mode
The MIPI bus controller uses the display command message to send a stream of pixel data to the display. The display should have a full frame long frame buffer to store all of the pixel data. Once the data is placed in the frame buffer of the display, the timing controller takes the data out of the frame buffer and automatically displays them on the screen. The MIPI bus controller does not need to refresh the display periodically.
Advantages and Disadvantages of Both Modes Each mode of operation has advantages and disadvantages in terms of cost and power consumption. The video mode display architecture does not require a frame buffer. However, the host periodically sends DSI video messages in high speed mode but consumes a large amount of average energy.
Ideally, when the display content does not change (or does not change often), the central processing unit of the display system should switch to a low power mode, and the link between the processor and the display will be activated when needed. Due to the need for the host to periodically refresh, some of the central processing unit and memory interface also need to remain active, which can make the system not achieve the best power budget.
On the other hand, the command mode display architecture allows the display to self-refresh directly across the entire frame buffer. However, integrating a full frame long frame buffer in a display is always costly, especially for high resolution displays that most users today require. This requires the interface chip to have a larger die size. Display manufacturers have also had to provide a display controller with a specific capacity frame buffer for each display resolution.
For video mode and command mode display architectures, it is often necessary to program the display controller's registers to set the corresponding display resolution, aspect ratio, and operating mode. MIPI does not define any standard protocols to access these internal registers, so different display manufacturers can customize their own dedicated command set.
In order to get rid of the conflicts between different manufacturer-specific display commands, some manufacturers prefer to have the display initialize itself so that the display does not require the configuration of the MIPI host controller to function properly. In this case, the display typically has a PROM memory that stores display parameters. This is very convenient, but the PROM also occupies a relatively large memory space.
Key factors for design considerations In order to achieve the best system utilization, equipment manufacturers also need to consider the following factors.
â— A conversion-efficient LDO power converter should be integrated inside the display and only an external supply voltage should be input to the display system.
â— For clocks generated by the internal PLL, an external input reference clock is usually required. The reference clock has a frequency from 32 kHz to a few megahertz. D-PHY is a scalable, low-power, high-speed physical layer standard that several MIPI interface standards will support. A reference clock is also required as a signal reference in some D-PHY timing parameters. In conjunction with the use of a reference clock, frequencies in the range of more than a dozen megahertz are very common. Typically, an internal oscillator generates a very low frequency clock as a reference clock that is fed back to the PLL and multiplies the frequency required to display the controller's D-PHY logic.
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