HD video chip technology development trend
With the rapid development of the application of high-definition video surveillance products in the past two years, especially in 2010, it is expected that in the next 1-2 years, the market demand for high-definition products will show a trend of blowout, and the increase in demand will bring on the one hand The demand for higher performance and more functions will also intensify differentiated competition. The high-definition video SoC, as the core part that can affect the two most, its technological evolution and performance improvement play a decisive role in the market status of high-definition video terminals.
Before discussing the development trend of high-definition video SoC technology, let's briefly analyze the current common architecture of high-definition video terminal (front-end) products. General high-definition video terminals are divided into three common parts: sensor, ISP, code compression or conversion, and some high-definition cameras will also include an intelligent processor.
1. The sensor refers to the CCD Sensor or CMOS Sensor that we often mention, such as ICX 445, ICX274, IMX035 / 036 of SONY, MT9M033 of ApTIna, OV2715 of Omnivison and so on. The main function is photoelectric conversion, which converts the optical signal into an electrical signal that can be recognized at the back end.
2. ISP, that is, the image processing part, 2A (AWB / AE) or 3A (AWB / AE / AF) that we often mention are all done here. In the traditional mode, a DSP or an FPGA is generally used to complete the post-processing of the image.
3. Code compression or conversion, after the sensor signal is processed by the ISP part, it is generally transmitted to the subsequent code compression or conversion part in a digital interface format such as SMPTE296M / BT.1120 and processed into a compressed TCP / IP signal or uncompressed HD -SDI signal.
4. The intelligent video analysis part is generally implemented by a single DSP. The DSP realizes video analysis functions such as behavior analysis, video diagnosis, and feature recognition. Due to the limitations of the algorithm performance and the difficulty of cross-platform migration, At present, such products are rarely used.
Traditionally, these parts are separated from each other, and different parts are completed by different chips. With the development of technology, more and more chip manufacturers have merged the latter two parts together, such as NSC's ASC8850 , Hisilicon's upcoming Hi3516, which makes the integration of high-definition video terminals higher and higher, in this context of the trend of convergence, high-definition video SoC technology development in multi-service integration will be the most critical point.
In the next 1-2 years, the author believes that the technological breakthroughs and development status of high-definition video SoC in power consumption, encoding performance, ISP, intelligent analysis, decoding and display will deeply affect the development of terminal products.
Lower power consumption
Unlike the previous DVR / DVS, where the encoding chip is generally at the back end, the high-definition encoding and ISP chips are both at the front-end camera section. If the power consumption of these chips results in a large amount of heat, DVR and DVS can be installed with heat sinks or cooling fans to ensure the normal operation of the device, but taking these measures in the camera part is obviously not the best choice, even The installation of these devices can reduce the temperature of the whole machine, and also virtually increase the point of failure and maintenance costs.
The ideal situation is that the power consumption of the high-definition terminal itself is reduced to the extent that it can work stably by natural heat dissipation. In this respect, the power consumption of the high-definition video chip itself needs to be lower, and it also requires that the power consumption of the matching FLASH, DDR and other peripheral chips also be reduced as much as possible. However, the reduction of power consumption and the improvement of performance are also a contradiction. A chip with a coding capacity of 1080P will require higher power consumption than a chip with a coding capacity of D1. How to solve this problem depends on the technical strength of chip manufacturers in this regard.
Higher encoding compression capacity
As the market's requirements for the resolution of high-definition video products continue to increase, the general 720P resolution has been a little stretched, and the demand of 2 million, 3 million or even 5 million is constantly emerging. Standard configuration, these pose greater challenges to the compression capability of HD video chips.
1. At present, most high-definition chips such as TI's DM368, HiSilicon Hi3515 / 3516, NXP's ASC8850, Fuhan's FH8736, etc. can achieve 1080P, that is, real-time encoding and compression of 2 million pixels can be achieved at 300 Real-time encoding is generally not possible at 10,000 and 5 million pixels. Currently, chips with higher performance can achieve 7-12 frames at 5 million pixels, which is already quite excellent. The future development trend is definitely to ensure the real-time encoding and compression of the main stream at 5 million or higher pixels. It is best to provide 1-2 real-time encoded D1 or 720P sub-streams. The high pixels are used for local preview or Storage, low pixels are used for remote network transmission.
2. Although H.264 has become the main compression format for video equipment for security since 2007, but as video equipment has been gradually applied in different industries, the MPEG4 and M-JPEG compression formats have gradually improved. There are many demands. At present, some chips can already support three compression formats of H.264, MPEG4 and M-JPEG at the same time. The difference is whether they can support the simultaneous transmission of 2 or 3 compressed format streams. Video chips can simultaneously provide three or more compressed format code streams, which is also a relatively urgent demand.
The fusion of image processing technology (ISP)
Image processing (ISP, Image Signal Processor) is an indispensable part of the camera. After the image is collected by CCD or CMOS, it needs to be post-processed to adapt to different environments and can be compared under different optical conditions. Good reproduction of scene details. Image processing includes many parts of the function, but the most important thing is that we often hear 2A and 3A, 2A refers to AWB (automatic white balance) and AE (automatic exposure), 3A is based on 2A plus AF (Auto Focus).
In traditional SD network cameras and most high-definition network cameras on the market, an independent DSP or FPGA processor is generally used to implement the ISP function. The signals processed by the DSP or FPGA enter the encoding chip again for compression processing. . Although this method has higher flexibility, allowing developers to have more combinations when choosing a solution, for the device, on the one hand, it increases the power consumption of the whole machine, and also increases the complexity of the device. If there is a more integrated chip solution, it is undoubtedly a better choice to integrate the ISP and the coding part.
In addition, most of the video chips with built-in ISP function now have more complete support for CMOS Sensors, and can directly connect to the main products of major Sensor manufacturers, but the support for CCD Sensors is relatively limited, and developers need to do secondary conversions. To add an additional CPLD or FPGA, in addition to reducing the development difficulty and cycle to a certain extent, the key BOM cost and overall power consumption are not much optimized.
Integrated smart video technology
After several years of development, intelligent analysis technology has gradually transformed the embarrassing situation of advanced technology and hopeless application. The older the more, the more popular it is in practical applications. With the advent of the high-definition era, the amount of information has doubled. Next, intelligent video technology has become an indispensable means.
The early intelligent analysis function was mainly implemented on the back end through the PC, and subsequent forms based on DVS or DVR appeared. With the advent of high-definition, the need for intelligent analysis to be integrated into the front end is very urgent. The improvement of chip performance provides for this demand. Feasibility.
According to the current application of intelligent video technology, it is expected that the following types of analysis algorithms will be first applied in high-definition front-end products: Video diagnostic algorithms are mainly used to determine whether the working status of front-end equipment is normal, whether there is blur, noise, or abnormality. Occlusion, video loss and other abnormal conditions; behavior analysis algorithm, mainly used to identify and judge the behavior of moving objects in video surveillance scenes; face detection and recognition algorithm, mainly used to detect facial features in surveillance scenes Out, identification and comparison; intelligent transportation algorithms, mainly used for traffic violation management, belong to a specific type of industry applications.
According to the current situation, the chip manufacturers do not yet have the mature conditions to directly build the above algorithm into the chip. The more feasible way is to reserve a higher frequency DSP or ARM core in the high-definition video chip, developers can own Choose to transplant some or all of the above algorithms to the DSP or ARM to form an intelligent camera with an intelligent algorithm.
Complete system supporting chips
The system supporting products mainly refer to the products used to monitor the back end. Many field experiences have shown that the promotion of HD must be done in a systematic way. When there is a high-quality HD front end, there must also be complete system supporting products to solve Important functions such as transmission, storage and display.
NVR and hybrid DVR chips, as the concept of high-definition began to gain popularity, NVR and hybrid DVR have gradually become necessary products for the system. The use of chips in NVR and hybrid DVR generally requires strong business processing capabilities, such as list management, storage management, and network management. At the same time, the performance requirements of the chip such as PCI are also high.
Decoding display chip, mainly used for high-definition image display, generally requires the chip to have good display performance, at the same time support as many outputs as possible, it is best to support HDMI or DVI digital high-definition output interface, and the output display resolution The minimum requirement is 1080P or even higher.
At present, the major chip manufacturers in the industry have realized the integration trend of high-definition video chips, and have invested a lot of energy in the research and development of a new generation of high-definition chips, whether it is the first to launch ASC8850 NXP and the DM368 TI, or the upcoming Hi3516 HiSilicon Semiconductors have already begun to make achievements on highly converged high-definition video chips, and some influential IC manufacturers are eager to try. I believe that with the efforts and promotion of chip manufacturers, combined with the market promotion and users of downstream terminal manufacturers Driven by demand, a new generation of highly integrated and highly integrated high-definition video chips will achieve greater and greater development and gradually become a mature industry.
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