Intermediate Converter and Point-of-Load Converter Design for Distributed Power Architecture
The distributed power architecture (DPA) continues to evolve to meet the system's higher demand for supply voltage, efficiency, current density, updated packaging, and BOM cost. However, design engineers still face pressure to reduce design costs and shorten development time. In addition, it must face the cost of improving the efficiency to avoid thermal management and maintaining reliability, as well as power sequencing control that supports multiple voltages. Power modules with these characteristics already appear on the market today.
Because the new generation of semiconductor manufacturing processes require lower voltages, system power supply design engineers must provide multiple operating voltages. To meet these requirements, DPA converts the typical 48V DC voltage on the backplane to an intermediate voltage. For telecommunication and industrial computing line cards up to 150W power, 8V is widely accepted as an ideal intermediate voltage. This does not require strict voltage regulation because the voltage regulation function can be transferred to a non-isolated point-of-load (POL) converter on each board.
Intermediate converter design
For engineers without extensive power supply design experience, the design of the intermediate converter is still a challenge. Based on International Rectifier (IR) IR2085S control IC chipset can solve the key design issues, design engineers can quickly design the required intermediate converter. This intermediate converter uses a DC bus transformer with no output voltage regulation, which reduces the cost and complexity of the isolated part by 50%. The control IC can be used in combination with the appropriate HEXFET power MOSFET pair in the transformer primary and secondary, plus some simple bias circuits. This configuration will provide the POL converter with an intermediate voltage.
Figure 1 shows the functional block diagram of the IR2085S control chip. The soft-start capacitor limits the inrush current at start-up and maintains the balanced pulse width of the high- and low-side MOSFETs during the entire start-up period. Its output is suitable for low-charge primary MOSFETs, and the device also prevents imbalance during transformer operation. Design engineers can use the programmability of the IR2085S switching frequency to optimize ripple currents and use components with low magnetic losses. Design engineers can also control dead-time to prevent current breakdown, and by limiting the secondary The body diode is turned on to maximize efficiency. The switching frequency and dead time can be individually adjusted by two external components. Other features include bootstrap design and VCC undervoltage lockout, high insensitivity to dv/dt to prevent conduction of the low-side MOSFET in the half-bridge, faster switching, and lighter design engineer burdens .
Eliminating the voltage regulator output at the mid-level removes the costly feedback circuitry and enables a relatively simple solution by reducing component count and board space. However, in some systems, the input voltage range may be from 36V to 72V. If the isolated converter design is based on a fixed ratio, such as the IR2085S scheme, the intermediate bus voltage will also change. This voltage is fed as input to the POL. Therefore, a simple architecture based on the IR2085S requires a POL converter that accepts both fixed and variable input voltages. The loss of complex efficiency may also be significant, which requires a highly efficient POL. For example, if the efficiency of both the intermediate converter and the POL converter is below 90%, the compounding efficiency will be as low as 81%.
The IR2085S-based intermediate converter can achieve up to 96% efficiency. When used in conjunction with a relatively efficient POL converter, the overall high efficiency can be achieved while simplifying the design and reducing costs.
POL converter design
In a POL design, choosing the most suitable sequence or tracking method for multi-voltage conduction is largely determined by the load specification. Sequential protocols are important because expensive devices such as NPUs and custom ASICs may be damaged if the power supply turns on and off. Therefore, design engineers must be able to implement an appropriate sorting scheme simply and effectively.
The three main tracking techniques are sequential, proportional, and simultaneous. In the case of sequential power supply conduction, the core voltage is first turned on to achieve the desired set value, and then the second supply voltage (ie, I/O level) starts to conduct; the proportional conduction method simultaneously turns on two The supply voltages, and the slope of the rise of each voltage are separately defined to achieve two different voltages at the same time; simultaneous conduction is the most common method, both voltages start simultaneously and rise with the same slope. As a result, the lower voltage (generally the IC core supply voltage) reaches the reference value before the higher I/O voltage.
Since wasted electrical energy is converted to thermal energy on a circuit board, inefficient POL converters pose thermal management issues that increase design costs and complexity. Therefore, the most efficient POL converters should be used in order to reduce power loss, and in turn obtain higher system reliability and guaranteed quality of service (QoS).
Integrated POL solution
To address these power supply design issues and simplify the work of design engineers, IR has developed two integrated POL converters that can be easily integrated into distributed power supply architectures, allowing design engineers to quickly implement a few external passive components It is easy to build a high-performance, two-phase, dual-output synchronous buck converter. Compared with discrete devices, this integrated solution can save 50% of board space and shorten design time. The IR solution also avoids the complex board layout issues associated with discrete device design and provides design engineers with 100% tested high-performance devices.
The iP1201 and iP1202 use IR's iPOWIR packaging technology to integrate PWM controller and driver functions, associated control and synchronous MOSFET switches, Schottky diodes, and input bypass capacitors in a single package. By setting power loss limits and safe operating area (SOA), these devices allow designers to obtain accurate thermal design of the PCB because there is no need to analyze in depth many of the first-stage, power-related variables caused by discrete power semiconductor devices. They also remove speculation related to second-order layout and stray parasitic loss effects, which are difficult to accurately determine at the beginning of design.
If the enclosure is controlled within the 90°C temperature range, the rated current per channel can reach 15A. Even without case temperature regulation, no heat sink or air cooling at the top, the product can still provide up to 11A of current. Multiple outputs can also be connected in parallel to an output with up to 30A. The iP1201 is suitable for applications with input voltages from 3V to 5.5V, while the iP1202 is suitable for designs with input voltages from 5.5V to 13.2V. Mixing these 180° out-of-phase outputs eliminates the effects of the two inductor ripple currents, so smaller output capacitors can be used.
By adding a capacitor for each individual soft-start pin, this scheme also provides power sequencing control for each output. To limit the inrush current at startup, the soft-start function can control the rise of the output voltage. As a result, by properly combining the two soft-start pins, the user can select the appropriate turn-on, turn-on or simultaneous turn-on.
Applications
Figure 2 shows a dual-output 1.5V/2.5V synchronous buck converter using the iP1202. At full load and an intermediate voltage of 8V, the efficiency is above 91%. The operating switching frequency range is 200kHz to 400kHz.
Other integrated features include: over-current and over-voltage protection, HICCUP, normal power indication, and thermal shutdown. These are the system-level features necessary for telecommunications and network equipment. This example provides a practical method to enhance the performance and design cycle of a distributed power architecture.
Nantong Boxin Electronic Technology Co., Ltd. , https://www.bosencontrols.com