Common IC package technology description

The following is a circuit diagram of [Common IC Package Technology Description]

Introduction to common IC packaging technology

1, BGA (ballgridarray)
One of the spherical contact display, surface mount packages. A spherical bump is formed on the back surface of the printed substrate in place of the lead, and the LSI chip is mounted on the front surface of the printed substrate, and then sealed by a molding resin or a potting method. Also known as a bump display carrier (PAC). The pin can exceed 200 and is a package for multi-pin LSI. The package body can also be made smaller than the QFP (four-sided pin flat package). For example, a 360-pin BGA with a 1.5mm center-to-center distance is only 31mm square; a 304-pin QFP with a 0.5mm center-to-center distance is 40mm square. And BGA doesn't have to worry about pin deformation like QFP. The package was developed by Motorola Inc. of the United States, and was first adopted in devices such as cellular phones, and is likely to become popular in personal computers in the United States in the future. Initially, the BGA has a pin (bump) center-to-center distance of 1.5mm and a pin count of 225. There are also some LSI manufacturers that are developing 500-pin BGAs. The problem with BGA is the visual inspection after reflow soldering. It is not clear whether an effective visual inspection method is available. Some believe that due to the large center distance of the weld, the connection can be considered stable and can only be handled by functional inspection. Motorola of the United States refers to a package sealed with a molded resin as OMPAC, and a package sealed by a potting method is called GPAC (see OMPAC and GPAC).
2, BQFP (quadflatpackagewithbumper)
Quad flat-lead package with pad. One of the QFP packages has protrusions (cushions) at the four corners of the package body to prevent bending deformation of the pins during shipping. US semiconductor manufacturers mainly use this package in circuits such as microprocessors and ASICs. The center of the pin is 0.635mm and the number of pins is from 84 to 196 (see QFP).
3, bump welding PGA (buttjointpingridarray)
Another name for surface mount PGA (see surface mount PGA).
4, C-(ceramic)
Indicates the mark of the ceramic package. For example, CDIP stands for ceramic DIP. It is a mark that is often used in practice.
5, Cerdip
Glass-sealed ceramic dual in-line package for circuits such as ECLRAM, DSP (Digital Signal Processor). Cerdip with glass window is used for UV-erasing EPROM and internal microcomputer circuit with EPROM. The center of the pin is 2.54mm and the number of pins is from 8 to 42. In japon, this package is represented as DIP-G (G is the meaning of a glass seal).
6, Cerquad
One of the surface mount packages, that is, a ceramic QFP sealed under the package, is used to package a logic LSI circuit such as a DSP. Cerquad with a window is used to encapsulate the EPROM circuit. The heat dissipation is better than that of plastic QFP, and it can tolerate 1.5 to 2W under natural air cooling conditions. But the packaging cost is 3 to 5 times higher than plastic QFP. The center distance of the pins is 1.27mm, 0.8mm, 0.65mm, 0.5mm, 0.4mm and other specifications. The number of pins is from 32 to 368.
7, CLCC (ceramicleadedchipcarrier)
A ceramic chip carrier with a lead, one of the surface mount packages, with leads drawn from the four sides of the package in a T-shape. A window with a UV erase type EPROM and a microcomputer circuit with an EPROM. This package is also known as QFJ, QFJ-G (see QFJ).
8, COB (chiponboard)
The chip-on-board package is one of the bare chip mounting technologies. The semiconductor chip is placed on the printed circuit board. The electrical connection between the chip and the substrate is realized by the wire stitching method. The electrical connection between the chip and the substrate is realized by the wire stitching method. Resin coverage to ensure reliability. Although COB is the simplest bare chip placement technology, its packaging density is far less than that of TAB and flip chip bonding.
9, DFP (dualflatpackage)
Double-sided pin flat package. It is another name for SOP (see SOP). I used to have this method before, but now I have basically not used it.
10, DIC (dualin-lineceramicpackage)
Another name for ceramic DIP (including glass seal) (see DIP).
11, DIL (dualin-line)
Another name for DIP (see DIP). European semiconductor manufacturers use this name more.
12, DIP (dualin-linepackage)
Dual in-line package. One of the plug-in packages, the leads are led out from both sides of the package, and the package materials are plastic and ceramic. DIP is the most popular plug-in package, and its application range includes standard logic IC, memory LSI, and microcomputer circuit. The center of the pin is 2.54mm and the number of pins is from 6 to 64. The package width is typically 15.2mm. Some packages with widths of 7.52 mm and 10.16 mm are called skinnyDIP and slimDIP (narrow body type DIP), respectively. However, in most cases, it is not differentiated and is simply referred to as DIP. In addition, ceramic DIP sealed with low melting glass is also known as cerdip (see cerdip).
13, DSO (dualsmallout-lint)
Double-sided pin small outline package. Another name for SOP (see SOP). Some semiconductor manufacturers use this name.
14, DICP (dualtapecarrierpackage)
Double-sided pin-loaded package. One of TCP (loaded package). The leads are fabricated on the insulating tape and pulled out from both sides of the package. Due to the TAB (Automatic On-Load Soldering) technology, the package is very thin. It is commonly used in liquid crystal display driver LSIs, but most of them are fixed products. In addition, a 0.5 mm thick memory LSI booklet package is in the development stage. In japon, the DICP is named DTP according to the EIAJ (japon Electromechanical Industry) standard.
15, DIP (dualtapecarrierpackage)
Ibid. The japon electromechanical industry standard naming DTCP (see DTCP).
16, FP (flatpackage)
Flat package. One of the surface mount packages. Another name for QFP or SOP (see QFP and SOP). Some semiconductor manufacturers use this name.
17, flip-chip
Reverse soldering chips. One of the bare chip packaging technologies is to form metal bumps in the electrode regions of the LSI chip, and then bond the metal bumps to the electrode regions on the printed substrate. The footprint of the package is essentially the same as the chip size. It is the smallest and thinnest of all packaging technologies. However, if the thermal expansion coefficient of the substrate is different from that of the LSI chip, a reaction occurs at the joint, thereby affecting the reliability of the connection. Therefore, it is necessary to reinforce the LSI chip with a resin and use a substrate material having substantially the same thermal expansion coefficient.
18, FQFP (finepitchquadflatpackage)
The small pin center is from the QFP. Usually refers to QFP with pin center distance less than 0.65mm (see QFP). Some conductor manufacturers use this name.
19. CPAC (globetoppadarraycarrier)
Another name for BGA in the US Motorola (see BGA).
20, CQFP (quadfiatpackagewithguardring)
Quad flat-lead package with guard ring. One of the plastic QFPs, the pins are masked with a resin protection ring to prevent bending deformation. Before the LSI is assembled on the printed circuit board, the pins are cut from the guard ring and made into a seagull wing shape (L shape). This package has been mass produced in Motorola, USA. The center of the pin is 0.5mm, and the number of pins is up to 208.
21, H-(withheatsink)
Indicates a mark with a heat sink. For example, HSOP stands for SOP with a heat sink.
22, pingridarray (surfacemounttype)
Surface mount PGA. Usually the PGA is a plug-in package with a lead length of about 3.4 mm. The surface mount PGA has a display-like pin on the underside of the package with a length from 1.5mm to 2.0mm. The mounting method is a method of bump welding with a printed substrate, and is therefore also referred to as a bump-welded PGA. Because the pin center distance is only 1.27mm, which is less than half of the plug-in type PGA, the package body can be made not very large, and the pin count is more than the plug-in type (250-528), which is a package for large-scale logic LSI. . The packaged substrate has a multilayer ceramic substrate and a glass epoxy printing base. Packaging with a multilayer ceramic substrate has been put to practical use.
23. JLCC (J-leadedchipcarrier)
J-shaped pin chip carrier. Refers to the window CLCC and the ceramic QFJ with window (see CLCC and QFJ). The name adopted by some semiconductor manufacturers.
24, LCC (Leadlesschipcarrier)
Leadless chip carrier. Refers to the surface mount package with no electrodes on the four sides of the ceramic substrate. It is a package for high speed and high frequency ICs, also known as ceramic QFN or QFN-C (see QFN).
25, LGA (landgridarray)
Contact display package. That is, a package having an array state electrode contact is fabricated on the bottom surface. Plug in the socket when assembling. Practically available, ceramic LGAs with 227 contacts (1.27 mm center-to-center) and 447 contacts (2.54 mm center-to-center) are used in high-speed logic LSI circuits. Compared to QFP, LGA can accommodate more I/O pins in a smaller package. In addition, since the impedance of the lead is small, it is suitable for a high-speed LSI. However, due to the complexity of the socket production and the high cost, it is basically not used very much now. It is expected that its demand will increase in the future.
26. LOC (leadonchip)
On-chip lead package. One of the LSI packaging technologies, the front end of the lead frame is a structure above the chip, and a bump is formed near the center of the chip, and is electrically connected by wire stitching. The chip accommodated in the same size package has a width of about 1 mm compared to the structure in which the lead frame is originally disposed near the side of the chip.
27. LQFP (lowprofilequadflatpackage)
Thin QFP. Refers to the QFP with a package body thickness of 1.4mm, which is the name used by the japon electronic machinery industry according to the new QFP form factor.
28, L-QUAD
One of the ceramic QFP. The package substrate is made of aluminum nitride, and the base thermal conductivity is 7 to 8 times higher than that of alumina, and has good heat dissipation properties. The packaged frame is made of alumina, and the chip is sealed by potting, thereby suppressing cost. It is a package developed for logic LSI that can tolerate W3 power under natural air cooling conditions. 208-pin (0.5mm center-to-center) and 160-pin (0.65mm center-to-center) LSI logic packages have been developed and started mass production in October 1993.
29, MCM (multi-chipmodule)
Multi-chip components. A package in which a plurality of semiconductor bare chips are assembled on a wiring substrate. According to the substrate material, it can be divided into three categories: MCM-L, MCM-C and MCM-D. MCM-L is an assembly using a conventional glass epoxy multilayer printed substrate. The wiring density is not so high and the cost is low. MCM-C is a component that uses a thick film technique to form a multilayer wiring, and a ceramic (alumina or glass ceramic) as a substrate, similar to a thick film hybrid IC using a multilayer ceramic substrate. There is no significant difference between the two. The wiring density is higher than MCM-L. MCM-D is a component in which a multilayer wiring is formed by a thin film technique, and ceramic (aluminum oxide or aluminum nitride) or Si or Al is used as a substrate. The wiring scheme is the highest among the three components, but the cost is also high.
30, MFP (miniflatpackage)
Small flat package. Another name for plastic SOP or SSOP (see SOP and SSOP). The name adopted by some semiconductor manufacturers.
31, MQFP (metricquadflatpackage)
A classification of QFPs in accordance with JEDEC (United States Joint Electronic Equipment Council) standards. Refers to a standard QFP with a center-to-pin distance of 0.65mm and a body thickness of 3.8mm to 2.0mm (see QFP).
32, MQDU (metalquad)
A QFP package developed by Olin Corporation of the United States. Both the substrate and the cover are made of aluminum and sealed with an adhesive. The power of 2.5W to 2.8W can be tolerated under natural air cooling conditions. Japon Shin Kong Electric Industrial Co., Ltd. was licensed to start production in 1993.
33, MSP (minisquarepackage)
The nickname of QFI (see QFI) is often referred to as MSP in the early stages of development. QFI is the name given by the japon Electromechanical Industry Association.
34, OPMAC (overmoldedpadarraycarrier)
Molded resin seals the bump display carrier. The name used by Motorola in the United States for molded resin sealed BGA (see BGA).
35, P-(plastic)
Indicates the mark of the plastic package. For example, PDIP stands for plastic DIP.
36, PAC (padarraycarrier)
Bump display carrier, another name for BGA (see BGA)
37, PCLP (printedcircuitboardleadlesspackage)
Printed circuit boards are leadless packaged. Japon Fujitsu's name for plastic QFN (plastic LCC) (see QFN). The center distance of the pins is 0.55mm and 0.4mm. Currently in the development stage.
38, PFPF (plasticflatpackage)
Plastic flat package. Another name for plastic QFP (see QFP). The name adopted by some LSI manufacturers.
39, PGA (pingridarray)
Display pin package. In one of the cartridge type packages, the vertical pins on the bottom surface are arranged in a display. The package substrate basically uses a multilayer ceramic substrate. In the case where the material name is not specifically indicated, most of them are ceramic PGAs for high-speed large-scale logic LSI circuits. higher cost. The pin center distance is usually 2.54mm and the number of pins is from 64 to 447. In order to reduce the cost, the package substrate can be replaced with a glass epoxy printed substrate. There are also 64 to 256-pin plastic PGAs. In addition, there is a short lead surface mount PGA (PGA) with a 1.27mm lead pitch. (See surface mount PGA).
40, piggyback
Load package. The ceramic package is equipped with a socket, and the shape is similar to DIP, QFP, QFN. Used to evaluate program confirmation operations when developing devices with microcomputers. For example, plug the EPROM into the socket for debugging. This kind of package is basically a fixed product, which is not very circulated on the market.
41, PLCC (plasticleadedchip carrier)
Plastic chip carrier with leads. One of the surface mount packages. The pins are drawn from the four sides of the package and are T-shaped, which is a plastic product. Texas Instruments is first used in 64k DRAM and 256k DRAM, and is now widely used in logic LSI, DLD (or logic devices) and other circuits. The center of the pin is 1.27mm and the number of pins is from 18 to 84. The J-shaped pin is not easily deformed and is easier to handle than the QFP, but the visual inspection after soldering is difficult. PLCC is similar to LCC (also known as QFN). In the past, the only difference between the two was that the former used plastic and the latter used ceramic. However, the J-lead package made of ceramic and the leadless package made of plastic (labeled as plastic LCC, PCLP, P-LCC, etc.) have disappeared. To this end, the Japon Electromechanical Industry Association decided in 1988 to refer to the package with the J-lead from the four sides as QFJ and the package with the electrode bump on the four sides as QFN (see QFJ and QFN).
42. P-LCC (plasticteadlesschipcarrier) (plasticleadedchipcurrier)
Sometimes it is another name for plastic QFJ, sometimes it is another name for QFN (plastic LCC) (see QFJ and QFN). Some LSI manufacturers use PLCC for leaded package and P-LCC for leadless package to show the difference.
43, QFH (quadflathighpackage)
Four-sided, thick, flat package. One type of plastic QFP, in order to prevent the package body from breaking, the QFP body is made thicker (see QFP). The name adopted by some semiconductor manufacturers.
44, QFI (quadflatI-leadedpackgac)
Four-sided I-shaped pin flat package. One of the surface mount packages. The pins are led out from the four sides of the package and are I down. Also known as MSP (see MSP). The mounting is soldered to the printed substrate. Since the pins have no protruding portions, the mounting area is smaller than QFP. Hitachi has developed and used this package for video analog ICs. In addition, japon's Motorola's PLLIC also uses this package. The center of the pin is 1.27mm and the number of pins is from 18 to 68.
45, QFJ (quadflatJ-leadedpackage)
Four-sided J-pin flat package. One of the surface mount packages. The pins are led out from the four sides of the package and are J-shaped downward. It is the name given by the japon electronic machinery industry association. The center of the pin is 1.27mm.
The materials are plastic and ceramic. Plastic QFJ is often referred to as PLCC (see PLCC) for microcomputers, gate displays, DRAM, ASSP, OTP and other circuits. The number of pins is from 18 to 84. Ceramic QFJ is also known as CLCC, JLCC (see CLCC). The windowed package is used for UV erase type EPROM and microcomputer chip circuit with EPROM. Pin count from 32 to 84
46, QFN (quadflatnon-leadedpackage)
Four-sided, leadless flat package. One of the surface mount packages. Now more called LCC. QFN is the name given by the japon Electromechanical Industry Association. The electrode contacts are arranged on the four sides of the package. Due to the absence of leads, the mounting area is smaller than QFP and the height is lower than QFP. However, when stress is generated between the printed substrate and the package, no relief can be obtained at the electrode contact. Therefore, the electrode contacts are difficult to make as many pins as the QFP, generally from about 14 to about 100. The materials are ceramic and plastic. When there is an LCC mark, it is basically a ceramic QFN. The center of the electrode contacts is 1.27 mm.
Plastic QFN is a low cost package of glass epoxy printed substrate. In addition to the 1.27mm center distance of the electrode contacts, there are two types of 0.65mm and 0.5mm. Such packages are also referred to as plastic LCC, PCLC, P-LCC, and the like.
47, QFP (quadflatpackage)
Four-sided pin flat package. One of the surface mount packages, the leads are drawn from four sides into a gullwing (L) type. The substrate is available in ceramic, metal and plastic. In terms of quantity, plastic packaging accounts for the vast majority. When no material is specifically indicated, it is mostly plastic QFP. Plastic QFP is the most popular multi-pin LSI package. It is used not only for digital logic LSI circuits such as microprocessors and gate displays, but also for analog LSI circuits such as VTR signal processing and acoustic signal processing. The center distance of the pins is 1.0mm, 0.8mm, 0.65mm, 0.5mm, 0.4mm, 0.3mm and other specifications. The maximum number of pins in the 0.65mm center-to-center specification is 304.
Japon refers to a QFP with a pin center distance less than 0.65 mm as QFP (FP). But now japon electronic machinery industry will re-evaluate the QFP's form factor. There is no difference in the center distance of the pins, but it is divided into QFP (2.0mm ~ 3.6mm thick), LQFP (1.4mm thick) and TQFP (1.0mm thick) according to the thickness of the package body.
In addition, some LSI manufacturers refer to QFPs with a pin center distance of 0.5 mm as shrink-type QFP or SQFP and VQFP. However, some manufacturers also refer to the QFP with a pin center distance of 0.65mm and 0.4mm as SQFP, which makes the name slightly confused. The disadvantage of QFP is that the pins are easily bent when the center distance of the pins is less than 0.65 mm. In order to prevent pin deformation, several improved QFP varieties have emerged. BQFP with a tree-finger cushion at the four corners of the package (see BQFP); GQFP with a resin guard ring covering the front end of the pin (see GQFP); set test bumps in the package body and prevent pin deformation The TPQFP can be tested in a dedicated fixture (see TPQFP). In terms of logic LSI, many development products and high-reliability products are packaged in multi-layer ceramic QFP. Products with a minimum center-to-center distance of 0.4mm and a maximum of 348 pins have also been introduced. In addition, glass-sealed ceramic QFPs are also available (see Gerqad).
48, QFP (FP) (QFPfinepitch)
Small center distance from QFP. The name specified by the japon electronic machinery industry standard. Refers to QFP with pin center distance of 0.55mm, 0.4mm, 0.3mm, etc. less than 0.65mm (see QFP).
49, QIC (quadin-lineceramicpackage)
Another name for ceramic QFP. The name used by some semiconductor manufacturers (see QFP, Cerquad).
50, QIP (quadin-lineplasticpackage)
Another name for plastic QFP. The name used by some semiconductor manufacturers (see QFP).
51, QTCP (quadtapecarrierpackage)
Four-sided pin on-board package. One of the TCP packages, which form pins on the insulating tape and are drawn from the four sides of the package. It is a thin package using TAB technology (see TAB, TCP).
52, QTP (quadtapecarrierpackage)
Four-sided pin on-board package. The name used by the japon electromechanical industry in April 1993 for the QTCP specification (see TCP).
53, QUIL (quadin-line)
Another name for QUIP (see QUIP).
54, QUIP (quadin-linepackage)
Four-column in-line package. The pins are led out from both sides of the package, and each other is staggered downward into four columns. The center of the lead is 1.27 mm. When the printed circuit board is inserted, the insertion center distance becomes 2.5 mm. Therefore, it can be used for standard printed wiring boards. It is a smaller package than the standard DIP. Japon Electric uses a variety of packages in microcomputer chips for desktop computers and home appliances. The materials are ceramic and plastic. The number of pins is 64.
55, SDIP (shrinkdualin-linepackage)
Shrinkage type DIP. One of the cartridge type packages has the same shape as the DIP, but the pin center distance (1.778mm) is smaller than DIP (2.54mm), hence the name. The number of pins is from 14 to 90. Also known as SH-DIP. The materials are ceramic and plastic.
56, SH-DIP (shrinkdualin-linepackage)
Same as SDIP. The name adopted by some semiconductor manufacturers.
57, SIL (singlein-line)
Another name for SIP (see SIP). European semiconductor manufacturers use the name SIL.
58. SIMM (singlein-linememorymodule)
Single column memory component. A memory assembly is provided with electrodes only near one side of the printed substrate. Usually refers to the component that is plugged into the socket. The standard SIMM has 30 electrodes with a center distance of 2.54 mm and a 72 electrode with a center distance of 1.27 mm. SIMMs with 1 Mbit and 4 Mbit DRAMs packaged in SOJ on one or both sides of a printed circuit board have been widely used in personal computers, workstations, and the like. At least 30-40% of the DRAM is assembled in SIMM.
59, SIP (singlein-linepackage)
Single in-line package. The leads are drawn from one side of the package and arranged in a straight line. The package is side-mounted when assembled onto a printed substrate. The pin center distance is usually 2.54mm and the number of pins is from 2 to 23, most of which are custom products. The shape of the package varies. Some packages that have the same shape as the ZIP are called SIP.
60, SK-DIP (skinnydualin-linepackage)
A type of DIP. Refers to a narrow body DIP with a width of 7.62 mm and a pin center distance of 2.54 mm. Often referred to collectively as DIP (see DIP).
61, SL-DIP (slimdualin-linepackage)
A type of DIP. Refers to a narrow body DIP with a width of 10.16mm and a pin center distance of 2.54mm. Often referred to collectively as DIP.
62, SMD (surfacemountdevices)
Surface mount devices. Occasionally, some semiconductor manufacturers classify SOP as SMD (see SOP).
63, SO (smallout-line)
Another name for SOP. Many other semiconductor manufacturers in the world use this nickname. (see SOP)
64, SOI (smallout-lineI-leadedpackage)
I-shaped pin small outline package. One of the surface mount packages. The pins are drawn downward from the two sides of the package in an I-shape with a center-to-center distance of 1.27 mm. The placement area is smaller than the SOP. Hitachi uses this package in analog ICs (motor drive ICs). The number of pins is 26.
65, SOIC (smallout-lineintegratedcircuit)
Another name for SOP (see SOP). Many semiconductor manufacturers abroad use this name.
66, SOJ (SmallOut-LineJ-LeadedPackage)
J-shaped pin small outline package. One of the surface mount packages. The pin is drawn down from both sides of the package in a J-shape, hence the name. Usually plastic products, mostly used in memory LSI circuits such as DRAM and SRAM, but most of them are DRAM. Many DRAM devices packaged in SOJ are mounted on SIMM. The center of the pin is 1.27mm and the number of pins is from 20 to 40 (see SIMM).
67, SQL (SmallOut-LineL-leadedpackage)
The name used for the SOP in accordance with the JEDEC (United States Electronic Equipment Engineering Committee) standard (see SOP).
68, SONF (SmallOut-LineNon-Fin)
SOP without heat sink. Same as the usual SOP. In order to indicate the difference in no heat sink in the power IC package, a NF (non-fin) mark is intentionally added. The name used by some semiconductor manufacturers (see SOP).
69, SOF (smallOut-Linepackage)
Small outline package. One of the surface mount packages, the leads are gull-winged (L-shaped) from both sides of the package. The materials are plastic and ceramic. Also called SOL and DFP. In addition to being used for memory LSIs, SOPs are also widely used in circuits such as ASSPs that are not too large. In areas where the input and output terminals do not exceed 10 to 40, SOP is the most widely used surface mount package. The center of the pin is 1.27mm and the number of pins is from 8 to 44.
In addition, SOPs with a pin center distance of less than 1.27 mm are also referred to as SSOPs; SOPs with an assembly height of less than 1.27 mm are also referred to as TSOPs (see SSOP, TSOP). There is also an SOP with a heat sink.
70, SOW (SmallOutlinePackage (Wide-Jype))
Wide body SOP. Used by some semiconductor manufacturers

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